1. Field of the Invention
The present invention generally relates to high speed data communications wherein signal information is processed both in digital and analog forms. More specifically, the invention relates to a digital to analog data converter integrated circuit, which solves problems associated with integration density, power consumption, and data transmission protocol compatibility for central office digital subscriber line circuit cards.
2. Discussion of the Related Art
With the advancement of technology, and the need for instantaneous information, the ability to transfer digital information from one location to another, such as from a central office to customer premises, has become more and more important.
In a digital subscriber line (DSL) system, data is transmitted from a central office to customer premises via a transmission line, such as a two-wire pair, and is transmitted from the customer premise to the central office as well, either simultaneously or in different communication sessions. The same transmission line might be utilized for data transfer by both sites or the transmission to and from the central office might occur on two separate lines. In its most general configuration, a DSL card at a central office is comprised of a digital signal processor (DSP) which receives information from a data source and sends information to an analog front-end (AFE). The AFE serves as the interface between an analog line, such as the two-wire pair, and the DSP. The AFE functions to convert digital data, from the DSP, into a continuous time analog signal when processing downstream data. Conversely, the AFE serves to convert an analog signal to digital data when processing upstream data.
As an important part of the aforementioned system responsible for proper transmission and reception of data in a broadband network, the AFE performs multiple functions in addition to converting a digital signal into a continuous time analog signal. However, the functionality of the AFE is particular to the specific DSL application considered, wherein factors such as signal bandwidth, data rate, data reach, signal quality, power budget, and different applicable standards determine the optimum AFE. In order to minimize application-specific implementations of digital-to-analog converters (DACs) across the many DSL applications, it is desired to create a high-performance configurable DAC.
Considering the many flavors of DSL applications, the adaptability problem becomes more apparent. Focusing on ADSL applications, there are a number of different implementation standards available including: DMT-FDM, DMT-EC, G.lite, CAP-RADSL, and ADSL over ISDN, hereinafter the aforementioned ADSL applications will be denoted xDSL. For each application, the optimum AFE configuration varies. Subsequently, the DAC implementation for each separate AFE configuration must vary appropriately.
Sigma-Delta modulation is a method used to perform both analog-to-digital and digital-to-analog conversions. It uses the concept of over-sampling and digital signal processing in order to achieve high resolution of the desired signal bandwidth. Various Sigma-Delta architectures exist with many used in instrumentation, speech, high-fidelity audio digitization, digital cellular radio, and integrated services digital network (ISDN) applications. Sigma-Delta modulation may also be employed to perform analog-to-digital (ADC) and DACs for higher frequency signals in a variety of communications systems, such as xDSL applications.
A Sigma-Delta based DAC is a common choice when both high resolution and low distortion are desired. The high resolution and low distortion requirements in xDSL applications make the Sigma-Delta architecture a natural starting point for high performance DAC designs. However, the Sigma-Delta methodology presents some problems when adapted to xDSL applications.
Most of the published Sigma-Delta DACs are used in audio applications where the signal bandwidth of interest is approximately 20 kHz. In audio applications, a high over-sampling ratio can be easily achieved. In xDSL applications, the signal bandwidth of interest increases from 20 kHz to approximately 1 MHz. Conversion of the Sigma-Delta DAC from an audio application to a xDSL application requires an increase in the sampling rate that makes designing for low power consumption and low signal distortion difficult. Decimating the input signal to the switched-capacitor (SC) filter reduces the speed requirements, but requires an additional finite impulse response (FIR) filter and an operational-amplifier (op-amp). As a result, prior art DACs in xDSL applications have not achieved the signal bandwidth requirements of multiple xDSL applications in a power-efficient manner.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. One significant advantage of the present invention is the ability to effectively reduce crosstalk without any knowledge of (or without making any assumptions about) the crosstalk or the disturber signal. This significantly differs from certain prior art systems, which either have knowledge of or make certain assumptions about the disturber signal. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a SINC filter for an oversampling Sigma-Delta digital to analog converter (OSDAC) having a cascaded construction that results in reduced sensitivity to capacitor mismatch. Specifically, the SINC filter circuit filter may be defined by a transfer function H(z), which is further defined by first constituent transfer functions H1(z) and H2(z). The constituent transfer functions may be implemented in a cascaded fashion. Preferably, one of the cascaded sections includes a resistor string that defines a plurality of reference voltages. A plurality of switching elements are configured to controllably switch these reference voltages to a capacitor of a tap.